The present invention relates generally to a high speed voltage shifter and phase splitter circuit.
FIGS. 1 and 2 together illustrate a prior art voltage level shifter for providing first and second phase outputs. In FIG. 1, an input voltage A1IN is applied to the voltage level shifter to produce a first phase output D. In FIG. 2, an input voltage A21N is applied to the voltage level shifter to produce a second phase output D2. The input voltage A1IN and the input voltage A21N are out of phase with each other.
Referring to both FIGS. 1 and 2, the respective input voltages A1IN and A21N are applied to input inverter stages coupled to a first voltage supply VDD. Node B2 is inverter delayed by a single inverter stage formed of P-channel field effect transistor (PFET) P1 and an N-channel field effect transistor (NFET) N1 and out of phase to A1IN in FIG. 1 or A21N in FIG. 2. Node BBB2 is buffer delayed by a pair of parallel inverters formed by P2, N2 and P3, N3 and is in phase with A1IN in FIG. 1 or A21N in FIG. 2. The input inverters NFETs N1 and N3 are connected to a common node labeled NET3 and to a respective pair of NFETs N5, N6 and N7, N8. Node NET 3 is coupled to a second voltage supply VDDQ via a pair of NFETs N9, N10. Output inverter stages formed of P11, N11, and P12, N12 coupled between a second voltage supply VDDQ via a pair of PFETs P13, P14 and ground via a pair of NFETs N13, N14. PFET P13 is always turned on by a low enable input ENBAR applied to the gate input. NFET N14 is always turned on by a high enable input ENN applied to the gate input. NFETs N6 and N8 are turned on by a high enable input ENN applied to the gate input, which together with NFETs N5 and N7 help to pull node NET3 low. Output inverter stages formed of P11, N11, and P12, N12 respectively receive a gate input of BBB2 and B2.
FIGS. 4, 5, and 6 illustrate voltage waveforms of the prior art voltage level shifter of FIGS. 1 and 2 with voltage shown relative the vertical axis and time shown relative to the horizontal axis. In FIG. 4, voltage waveforms A1IN, B2, BBB2, and NET3 are illustrated. FIG. 5 provides an expanded view of the voltage waveforms A1IN, B2, BBB2, and NET3 of FIG. 4. FIG. 6 illustrates the input voltage waveform A1IN together with outputs D and D2 of FIGS. 1 and 2. The prior art level shifter has an operational time delay that is much greater than can be used effectively for high speed applications. Another problem with the prior art level shifter is that balanced output is not provided. As illustrated in FIG. 6, with VDDQ of 1.5 Volts, the cross point of outputs D and D2 is at about 1.07 Volts, rather than VDDQ/2 or 0. 75 Volts.
A need exists for an improved high speed voltage shifter and phase splitter circuit. It is desirable to provide such a voltage shifter and phase splitter circuit that achieves balanced outputs as well as a small delay. It is also desirable to provide such a voltage shifter and phase splitter circuit that minimizes the number of devices required to produce two phases so that less physical area is required.
A principal object of the present invention is to provide an improved high speed voltage shifter and phase splitter circuit. Other important objects of the present invention are to provide such voltage shifter and phase splitter circuit substantially without negative effect and that overcomes many of the disadvantages of prior art arrangements.
In brief, a high speed voltage level shifter and phase splitter circuit is provided. The voltage level shifter and phase splitter circuit includes an input signal. A first input inverter stage receives the input signal and provides an inverted delayed out of phase signal to the input signal. A buffer stage receives the input signal and provides a buffered delayed in phase signal to the input signal. A first constant current source is coupled between the first input inverter stage and the buffer stage. A first output inverter stage is coupled to the first constant current source and provides a voltage level shifted and out of phase signal to the input signal. A second constant current source is coupled between the first input inverter stage and the buffer stage having an opposite polarity as the first constant current source. A second output inverter stage is coupled to the second constant current source and providing a voltage level shifted and in phase signal to the input signal.